1. Description of the Invention
This invention relates to phase detectors.
More particularly the invention relates to phase detectors suitable for use in phase locked loop arrangements of the kind adapted to produce a reference signal locked to the frame repetition frequency of a multiplex time division signal comprising frames consisting of a plurality of channels containing analogue data and a pair of adjacent channels containing pedestal voltages of different values. The different valued pedestal voltages provide a voltage transition for synchronising purposes, i.e. a sync edge. Digital or analogue data may also be encoded into the channels containing the pedestal voltages, providing the sync edge is retained.